Some semiconductor package substrates include a plurality of pillars for connecting solder bumps of a semiconductor die to the substrate. After a reflow process, solder joints are formed between the die and the pillars, so that the die is bonded to the pillars and the electrical connection therebetween is secured. The pillars may be formed by electroplating. However, unpredictable and variable plating parameters in the plating bath often lead to over-plating or under-plating, which, in turn, results in the top surfaces of the plated pillars not being coplanar. The lack of coplanarity negatively affects the solder joint reliability after packaging. Fine pitch solder bumps, wafer level packaging (WLP) and large-scale substrates are particularly sensitive to this issue. The lack of coplanarity can cause a non-uniform electric current density distribution, which is especially serious on micro-scale patterns. This common non-uniform electric current density distribution is not affected by only one factor but by various plating parameters consisting of plating bath design, chemical additives, magnitude of current density, use of current type, distance between cathode and anode, agitation method, chemical maintenance, pre-cleaning solution, configurations, arrangements and volumes of patterns, high aspect ratio, etc. It is difficult to control the height deviation to within 5 μm across the whole substrate, particularly if there is a need to add leveling agent, wetting agent, or brightener to the plating bath.